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The Multiply-ACCUMULATE (MAC) device is a familiar digital block that is widely used for numerous data-intensive applications in microprocessors and in the digital signal processors. In many filters, MAC units can effectively accelerate orthogonal frequency-division multiplexing algorithms. A two-cycle multiply-accumulated (MAC) high speed and an energy-efficient design is proposed that requires two supplementary numbers, bits of accumulator guard and saturated circuitry. The first stage consistsofonly part-product generation circuits and a reduction tree, whereas the second stage integrates all other functionality with a single sign extension approach. The proposed design is extendedto produce a double-throughput MAC (DT-MAC) device that either executes or accumulates efficient multiplying operations. A simpler method of combining the two binary numbers is achieved using adders to reduce processing time. The proposed adder is constructed with a KoggeStone Adder (KSA) and Brent-Kung (BK) parallel to the carry-look style adder in the MAC accumulator. It performs in a minimum period of time andit measures the fastest addition and is commonly used in industry for the achievement of highly efficient arithmetic circuits. In the KSA the carriers are computed in parallel. Chip area is reduced in BK. The proposed MAC with parallel prefix adder results in power reduction and high throughput.