Design and Analysis of Dynamic Comparator based on Cross Coupled Inverters for Low Power and High-Speed ADC Applications

Abstract

Now a days CMOS dynamic comparator mostly used for the analog to digital (A/D) conversion applications, because of high speediness and power minimization, low immune to noise characteristics. The proposed topology described in this project i.e., dynamic comparator based on cross coupled differential pairs inverters as the latching stage, which affords a positive feedback and gives extraordinary improvement switchable current sources. It will work with less static power consumption, higher speediness and minimize the area. The conventional latching level has two transistors with zero voltage in between gate to sources, which minimize the total effective trans conductance of latching level. In this paper dynamic comparators using a cross-coupled inverters, decrease the power consumption also very much useful for high-speed Analog to Digital conversion application. The dynamic comparator circuit designed with 0.13 m CMOS technology by using Mentor Graphics Tool for simulating transient response and dc response results. Layout of the recommended  cross coupled dynamic comparator has been done in Mentor graphics EDA tool and finally compared the schematic and layout using layout vs schematic (LVS).