Design Optimization of Low power VLSI Circuits in Deep Submicron Technology

Abstract

This paper explores the effect of scaling for low energy and high efficiency of demand and as difficulties of SOI circuits designing. This paper presents the design of a 45 nm SOI MOSFET and surveys the effect on various instrument parameters of the variant of channel doping and gate oxide thickness. Characteristics have been acquired for the suggested MOSFET by considering the most helpful channel doping and TOX values. The Visual  TCAD system of used to simulate devices and extract parameters.