Dr. Saminathan V., Jagadesh P. J., Sathosh Kumarr E., Sathish S., Sivasankaran S. Implementation of 16-Bit Vedic Multiplier in Alu Using Verilog. Annals of RSCB [Internet]. 2021Apr.24 [cited 2024Apr.30];:9968-75. Available from: https://annalsofrscb.ro/index.php/journal/article/view/3747