Dr. Saminathan V., Jagadesh P. J., Sathosh Kumarr E., Sathish S., Sivasankaran S. “Implementation of 16-Bit Vedic Multiplier in Alu Using Verilog”. Annals of the Romanian Society for Cell Biology (April 24, 2021): 9968–9975. Accessed April 30, 2024. https://annalsofrscb.ro/index.php/journal/article/view/3747.