Implementation of High Speed FFT using Reversible Logic Gates for Wireless DSP Applications

Abstract

The proposed FFT is constructed using Modified Reversible Logic Gates logic using Ripple carry Adder and its performance is compared with the existing Multiplier Circuits. This type of adders can be applied in the field of digital image processing and signal processing where importance is given to accuracy. The design will be implemented and simulated using Xilinx-ISE-Simulator and performance will be tested. The proposed Reversible Logic Gates logic implemented in Ripple carry adder system using xor logic has an accuracy of 99.98% and power consumption has reduced by more than 75%. Implementation of Modified Reversible Logic Gates logic using xor logic is done using the Xilinx-ISE-simulator tool. Using this adder we have designed an Multiplier based on the Vedic mathematics computation using reversible logic gates. The Vedic multiplier is implemented in FFT, which uses Urdhva Tiryabhyam, Nikhilam Navatashcaramam Dashatah, and Anurupye Vedic mathematical algorithms. The N point DFT is computed by using efficient Fast Fourier transform (FFT) algorithm. It’s necessary for a multiplier to be fast and power efficient in order to make this process rapid and simple. It is used to solve partial differential equations and also to perform convolution operations. © 2020 Elsevier Ltd. All rights reserved. Selection and/or Peer-review under responsibility of International Conference on Mechanical, Electronics and Computer Engineering.