A PTL based power efficient ALU block using 45nm Technology

Abstract

Pass Transistor Logic is one of the best among the available methods to implement circuits where low power plays a major role. This logic nullifies the leakage power in total power consumed by the circuit. This paper deals with the design of 4-Bit ALU. The proposed ALU is capable of performing AND, OR, XNOR, XOR, Sum, Carry operations of two 4-Bit binary numbers. A 4-Bit adder is designed by cascading Half-adder and Full-adder circuits to obtain sum, carry. For the purpose of selecting the desired operation 8:1 Multiplexers are used. The simulation result consists of power calculated for 4-Bit ALU,1-Bit Logical Block, Multiplexers. For the simulation of the circuits we have used virtuoso platform of Cadence tool with 45nm CMOS technology and supply voltage of 1V.