Ultra-Low Energy-Efficient Programmable Array Accelerator and Compiling Flows for the Near Sensor

Abstract

We present the ultra-low-energy accelerators for near-sensor handling Coarse grained reconfigurable arrays (CGRAs). The Integrated Programmable Array Accelerator (IPA) in application kernels containing complex controller flows, with an overhead of powerful cutting-edge approaches, provides a new architecture, model execution, and compilation flow. In order to improve performance and productivity, our research builds on IPA architecture with common memory access in this paper. Compared to the most advanced partial and full prediction methods, we are making maximum energy and efficiency gains. Compared to the center of ultra-low capacity near-sensor processing via a large number of near sensor kernels, the proposed accelerator would achieve high energy efficiency.